EV & Fast Charging
High-voltage and low-resistance epi layers for electric vehicle powertrains and fast-charging systems. Optimized for 650V-1700V SiC MOSFETs and JBS diodes, featuring high thickness uniformity of ≤4% and precise doping profiles.
Select a wafer type to view detailed specs
High-voltage and low-resistance epi layers for electric vehicle powertrains and fast-charging systems. Optimized for 650V-1700V SiC MOSFETs and JBS diodes, featuring high thickness uniformity of ≤4% and precise doping profiles.
Reliable epi wafers designed for harsh-environment energy conversion and heavy machinery. Engineered for high-power SiC MOSFETs, SBDs, and 1200V+ power modules in solar inverters, energy storage, and rail transit systems.
Enabling ultra-low switching loss epi layers for high-density server power supplies (PSUs). Tailored for Trench MOSFETs and high-efficiency rectifiers, delivering low BPDs and minimal surface roughness for maximum power efficiency.
Thick epitaxial layers for next-generation smart grids and energy storage systems (ESS). Supporting 10kV+ IGBTs, GTOs, and PN junctions with our ultra-thick epi capability ranging from 30 to 200µm.
Quick answers on material selection, customization, testing and ordering.
For standard 4H-SiC homoepitaxy, carrier concentration can be controlled over approximately 1×10¹⁴ to 1×10¹⁹ cm⁻³. This depends on the conductivity type (N-type or P-type) and your specific epi design.
For standard 4H-SiC homoepitaxy, thickness uniformity can be controlled to approximately ≤10%. For selected P-type SiC epi structures, uniformity can reach ≤4%. Actual performance depends on wafer size, epi thickness, and structure.
Yes. PWG can develop custom multilayer epitaxial structures, including buffer layers, current-spreading layers, channel layers, barrier layers, and other device-specific structures.
Yes. We offer 30–200 µm thick SiC epitaxial layers for ultra-high-voltage applications (up to 10kV+). Thickness, doping concentration, and uniformity are optimized according to your target breakdown voltage.
We implement strict epi process control to minimize Basal Plane Dislocations (BPDs) and Stacking Faults (SFs). Typical defect density is maintained at industry-leading levels to ensure high device yield and reliability. Full mapping data is available upon request.
Technical Inquiry
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No. 1389, Lianmei Road, Lianhua Industrial Zone, Tong’an, Xiamen, Fujian 361100, China
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